Design and Analysis of an Area and Power Efficient Programmable Delay Cell

This work presents a programmable delay cell in 90- nm CMOS technology and 1.1 V supply voltage Vdd. The delay cell provides the variable delay option with eight different modes M0-M7 and maintaining a stable output. Neglecting bond pad and die decoupling capacitor, the structure occupies 0.009 mm(2). The proposed delay cell consumes only 0.671 mu W at MO and 3.88 mu W at M7. Besides, for NN process the delay corresponding to the modes ranges between 0.69 - 5.54 mu s at 1.1 V and 27 degrees C. The results of Monte Carlo study show that power and delay changes minimally for MO and are equal for M7 to that obtained at NN.