Design and Analysis of an Area and Power Efficient Programmable Delay Cell

被引：0

作者：

Chakraborty, Kuntal ^{[1
]}

Pandey, Jai Gopal ^{[2
]}

Mondal, Abir J. ^{[1
]}

机构：

[1] NIT Arunachal Pradesh, Elect & Commun Engn, Jote, India

[2] CSIR CEERI, Integrated Circuits & Syst Grp, Pilani, Rajasthan, India

来源：

PROCEEDINGS OF THE 37TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, VLSID 2024 AND 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, ES 2024 | 2024年

关键词：

programmable delay; delay chain; multiplexer; channel length modulation coefficient; ELEMENT;

D O I：

10.1109/VLSID60093.2024.00010

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work presents a programmable delay cell in 90- nm CMOS technology and 1.1 V supply voltage Vdd. The delay cell provides the variable delay option with eight different modes M0-M7 and maintaining a stable output. Neglecting bond pad and die decoupling capacitor, the structure occupies 0.009 mm(2). The proposed delay cell consumes only 0.671 mu W at MO and 3.88 mu W at M7. Besides, for NN process the delay corresponding to the modes ranges between 0.69 - 5.54 mu s at 1.1 V and 27 degrees C. The results of Monte Carlo study show that power and delay changes minimally for MO and are equal for M7 to that obtained at NN.

引用

页码：31 / 36

页数：6

共 50 条

[31] Design And Implementation Of Area- Delay-Power Efficient CSLA Based 32-Bit Array Multiplier
Afreen, N. Fahmina
Basha, M. Mahaboob
Das, S. Mohan
2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2017, : 1578 - 1582
[32] Power, Delay and Area Efficient Self-Timed Multiplexer and Demultiplexer Designs
Balasubramanian, P.
Edwards, D. A.
DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, : 173 - 178
[33] Novel power-delay-area-efficient approach to generic modular addition
Patel, Riyaz A.
Benaissa, Mohammed
Powell, Neil
Boussakta, Said
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (06) : 1279 - 1292
[34] Design And Analysis Of Various Slice Reduction Algorithm For Low Power And Area Efficient Fir Filter
Umasankar, A.
Vasudevan, N.
2013 INTERNATIONAL CONFERENCE ON CURRENT TRENDS IN ENGINEERING AND TECHNOLOGY (ICCTET), 2013, : 259 - 263
[35] Design and Analysis of Low Power, Area Efficient Skip Logic for CSKA Circuit in Arithmetic Unit
Vijayakumar, S.
Jayaprakasan, V.
Korah, Reeba
2018 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS), 2018, : 162 - 166
[36] Design of Optimum Power, Delay Efficient Level Shifter for Biomedical Applications
Thomas, Saumya
Varghese, George Tom
2017 INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING, INSTRUMENTATION AND CONTROL TECHNOLOGIES (ICICICT), 2017, : 219 - 222
[37] DESIGN OF AN EFFICIENT PARALLEL COMPARATOR ARCHITECTURE FOR LOW POWER DELAY PRODUCT
Gupta, Mangal Deep
Chauhan, Rajeev Kumar
ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING, 2021, 19 (02) : 155 - 167
[38] Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder
Gokhale, G. R.
Gokhale, S. R.
2015 IEEE INTERNATIONAL CONFERENCE ON INFORMATION PROCESSING (ICIP), 2015, : 295 - 300
[39] Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters
Chen, Jiajia
Chang, Chip-Hong
Ding, Jiatao
Qiao, Rui
Faust, Mathias
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (02) : 712 - 722
[40] Digitally programmable delay element: Design and analysis (vol 11, pg 871, 2003)
Maymandi-Nejad, M
Sachdev, M
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (10) : 1126 - 1126

← 1 2 3 4 5 →