EVALUATION AND CONTROL OF DEVICE DAMAGE IN HIGH-DENSITY PLASMA-ETCHING

The effects of polysilicon etch plasma conditions on metal-oxide-semiconductor (MOS) capacitor breakdown and n-channel MOS transistor (NMOS) performance have been investigated. A high density electron cyclotron resonance (ECR) plasma source with multipolar magnetic confinement was integrated into a full NMOS process flow. The polysilicon etch plasma process parameters for designed experiments were microwave power, overetch time, rf bias, and plasma radial uniformity. MOS capacitor leakage currents increase with longer polysilicon edge lengths on gate oxide, higher ion density, and higher ion energy during the polysilicon overetch step. Lower NMOS transistor transconductance and higher threshold voltages correlate with longer overetch times and high microwave power and rf bias during the overetch step. Device performance degradation increases with decreasing channel length, and the exposure of the source and drain oxide edges to a high density flux is thought to be the main cause for observed degradation. A high rate, selective, and low damage polysilicon etch process can be obtained using a high density (>10(11) cm-3) and moderate ion energy (<30 eV) ECR discharge, with moderate power and zero applied rf bias during the overetch step.