DEVICE CHARACTERIZATION OF A HIGH-PERFORMANCE 0.25-MU-M CMOS TECHNOLOGY

The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 mum CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could operate at 2.5 V supply voltage. The delay per stage of a non-optimized 51-stage ringoscillators fabricated in the 0.25 mum process was 62 ps at 2.5 V supply voltage which is a 1.5 times improvement over the delay obtained in a 0.5 mum CMOS technology at 3.3V.