Bit-Level Pipelined 2-D Digital Filters for Real-Time Image Processing

Bit-level systolic arrays for real-time 2-D FIR and IIR filters am presented. Two-dimensional Iteration and retiming techniques an depicted to illustrate block pipeline 2-D IIR filters, which guarantee high throughput operation for real-time applications. The block (parallel) systolic architectures are refined down to the bit level. By doing so we increase the filter's throughput rate as well as decrease the filter's development and manufacturing costs. We Improve the AP figure from O(N(2)W(3)) by the previous design to O(N(2)W(2)), Le., by a factor of O(W). Pipelining at the bit level is the major reason for this improvement. Another advantage of our design Is that It has a simpler wire routing and control circuitry. In summary. our systolic-array realizations are 1) more cost effective; 2) more regular structurally; 3) composed of bit-level cells and latches; 4) fully pipelined at The bit level.