共 50 条
- [41] Simplified bit parallel systolic multipliers for special class of Galois field (2m) with testability IET COMPUTERS AND DIGITAL TECHNIQUES, 2010, 4 (05): : 428 - 437
- [43] Single error correcting finite field multipliers over GF(2m) 21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 33 - +
- [44] Low complexity sequential normal basis multipliers over GF(2m) 16TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2003, : 188 - 195
- [46] Compact FPGA-based hardware architectures for GF(2m) multipliers 16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013), 2013, : 649 - 652
- [47] Pipelined systolic multiplier for finite fields GF(2m) INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, PROCEEDINGS, 1999, : 1224 - 1229
- [49] An efficient Systolic multiplier for finite fields GF(2m) PDPTA'2001: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, 2001, : 1366 - 1371
- [50] Efficient reconfigurable implementation of canonical and normal basis multipliers over Galois fields GF(2m) generated by AOPs JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 42 (03): : 285 - 296