共 50 条
- [21] Design and analysis of low-power and area efficient N-bit parallel binary comparator Analog Integrated Circuits and Signal Processing, 2017, 92 : 225 - 231
- [22] Stability of n-Bit Generalized Full Adder Circuits (GFAs). Part II FORMALIZED MATHEMATICS, 2008, 16 (01): : 73 - 80
- [24] Bit-Parallel Arithmetic Implementations over Finite Fields GF(2m) with Reconfigurable Hardware Acta Applicandae Mathematica, 2002, 73 : 337 - 356
- [25] A Compact Design of n-Bit Ripple Carry Adder Circuit using QCA Architecture 2015 IEEE/ACIS 14TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS), 2015, : 155 - 160
- [26] OPTOELECTRONIC BUTTERFLY INTERCONNECTION ARCHITECTURE OF MODIFIED SIGNED-DIGIT ARITHMETIC SYSTEMS - FULLY PARALLEL ADDER AND SUBTRACTER APPLIED OPTICS, 1994, 33 (29): : 6755 - 6761
- [27] OPTICAL IMPLEMENTATION OF PARALLEL DIGITAL ADDER AND SUBTRACTOR APPLIED OPTICS, 1990, 29 (14): : 2099 - 2106
- [28] A Compact Realization of an n-Bit Quantum Carry Skip Adder Circuit with Optimal Delay 2014 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS), 2014, : 270 - 277
- [29] A parallel optical implementation of arithmetic operations OPTICS AND LASER TECHNOLOGY, 2013, 49 : 173 - 182
- [30] DESIGN AND ANALYSIS OF IMPROVED LOW POWER AND HIGH-SPEED N-BIT ADDER 2021 INTERNATIONAL CONFERENCE ON DECISION AID SCIENCES AND APPLICATION (DASA), 2021,