THE COUNTERFLOW PIPELINE PROCESSOR ARCHITECTURE

被引：60

作者：

SPROULL, RF ^{[1
]}

SUTHERLAND, IE ^{[1
]}

MOLNAR, CE ^{[1
]}

机构：

[1] WASHINGTON STATE UNIV,INST BIOMED COMP,PULLMAN,WA 99164

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1994年 / 11卷 / 03期

关键词：

D O I：

10.1109/MDT.1994.303847

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In a counterflow pipeline processor, instructions and results flow in opposite directions through a pipeline, interacting as they pass. Although detailed simulations of a complete processor design are not yet available, the architecture promises regularity in chip layout, local control to avoid performance limitations, and simplicity that may lead to provably correct designs. Moreover, CFPP designs allow asynchronous implementations more readily than conventional pipeline designs.

引用

页码：48 / 59

页数：12

共 50 条

[41] The Cell processor architecture
Kahle, J
MICRO-38: Proceedings of the 38th Annual IEEE/ACM International Symposiumn on Microarchitecture, 2005, : 3 - 3
[42] Persistent Processor Architecture
Zeng, Jianping
Jeong, Jungi
Jung, Changhee
56TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO 2023, 2023, : 1075 - 1091
[43] The superthreaded processor architecture
Tsai, JY
Huang, J
Amlo, C
Lilja, DJ
Yew, PC
IEEE TRANSACTIONS ON COMPUTERS, 1999, 48 (09) : 881 - 902
[44] A reconfigurable processor architecture
Niyonkuru, A
Eggers, G
Zeidler, HC
FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS: RECONFIGURABLE COMPUTING IS GOING MAINSTREAM, 2002, 2438 : 1160 - 1163
[45] Idempotent Processor Architecture
de Kruijf, Marc
Sankaralingam, Karthikeyan
PROCEEDINGS OF THE 2011 44TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO 44), 2011, : 140 - 151
[46] VLSI PROCESSOR ARCHITECTURE
HENNESSY, JL
IEEE TRANSACTIONS ON COMPUTERS, 1984, 33 (12) : 1221 - 1246
[47] Power efficient processor architecture and the cell processor
Hofstee, HP
11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 2005, : 258 - 262
[48] Hardened Processor Architecture
Mach, Jan
Kohutka, Lukas
Cicak, Pavel
2023 30TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM, MIXDES, 2023, : 176 - 182
[49] Multimedia processor architecture
Ikedo, T
Martens, WL
IEEE INTERNATIONAL CONFERENCE ON MULTIMEDIA COMPUTING AND SYSTEMS, PROCEEDINGS, 1998, : 316 - 325
[50] Design of a 32-Bit RISC processor with dual-issue and dual-pipeline architecture
Huang, Xiaoping
Fan, Xiaoya
Zhang, Shengbing
Shi, Liwen
Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 2011, 29 (01): : 6 - 11

← 1 2 3 4 5 →