THE COUNTERFLOW PIPELINE PROCESSOR ARCHITECTURE

被引：60

作者：

SPROULL, RF ^{[1
]}

SUTHERLAND, IE ^{[1
]}

MOLNAR, CE ^{[1
]}

机构：

[1] WASHINGTON STATE UNIV,INST BIOMED COMP,PULLMAN,WA 99164

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1994年 / 11卷 / 03期

关键词：

D O I：

10.1109/MDT.1994.303847

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In a counterflow pipeline processor, instructions and results flow in opposite directions through a pipeline, interacting as they pass. Although detailed simulations of a complete processor design are not yet available, the architecture promises regularity in chip layout, local control to avoid performance limitations, and simplicity that may lead to provably correct designs. Moreover, CFPP designs allow asynchronous implementations more readily than conventional pipeline designs.

引用

页码：48 / 59

页数：12

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