共 50 条
- [1] An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects 23RD INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2010, : 411 - +
- [2] Schmitt Trigger as an Alternative to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects TENCON 2009 - 2009 IEEE REGION 10 CONFERENCE, VOLS 1-4, 2009, : 922 - +
- [3] Encoding with repeater insertion for minimizing delay in VLSI interconnects 6TH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2006, : 205 - +
- [5] An improved RC model for VLSI interconnects with applications to buffer insertion Analog Integrated Circuits and Signal Processing, 2014, 79 : 105 - 113
- [7] Reduction of Crosstalk Noise and Delay in VLSI Interconnects Using Schmitt Trigger as a Buffer and Wire Sizing ADVANCES IN COMPUTING AND INFORMATION TECHNOLOGY, VOL 3, 2013, 178 : 677 - 686
- [9] Leveraging delay slack in flip-flop and buffer insertion for power reduction ISQED 2004: 5TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2004, : 69 - 74
- [10] An Optimization Algorithm for Simultaneous Routing and Buffer Insertion with Delay-Power Constraints in VLSI Layout Design PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014), 2015, : 357 - +