AN ASIC DESIGN FOR EDGE-DETECTION IN REAL-TIME

An ASIC design for image processing which can implement edge, line and point detection on a single VLSI chip in real time is reported here. The design is based on a set of orthogonal Chebyshev polynomial based operators and consists of a pipelined array of registers and adders with a simple and modular structure which is easily amenable to VLSI implementation. The design has been implemented using VTI design tools on a SUN workstation and the estimated overall chip size is 10.18 mm x 6.92 mm for 1.5 mum CMOS process utilizing about 84,000 transistors. Although the hardware requirements are relatively low, real time processing of a 512 x 512 pixel image can be realized at a clock rate of 8 MHz.