A 32-BIT RISC CPU IMPLEMENTED IN GAAS

被引：0

作者：

GEIDEMAN, WA ^{[1
]}

NIEDERLAND, RA ^{[1
]}

HARRINGTON, DL ^{[1
]}

机构：

[1] MCDONNELL DOUGLAS ELECTR SYST CO,HUNTINGTON BEACH,CA 92647

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1990年 / 30卷 / 1-5期

关键词：

D O I：

10.1016/0165-6074(90)90229-3

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the architecture, design and performance of a 32-bit RISC microprocessor chip implemented using enhancement mode junction field effect transistor (JFET) technology in GaAs. The chip operated at a maximum speed in excess of 80 MHz with one instruction per cycle. © 1989.

引用

页码：127 / 133

页数：7

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