A 55 nm CMOS Delta Sigma fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated Delta Sigma fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network (WLAN) transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm (2) excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6 degrees. The proposed synthesizer consumes a total power of 15.6 mW.