SELF-TIMED LOGIC-CIRCUITS

被引：8
|
作者：
POOLE, NR
机构：
来源：
ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL | 1994年 / 6卷 / 06期
关键词：
D O I：
10.1049/ecej:19940604
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Self-timed and asynchronous design techniques are currently proposed as a vehicle for pushing digital integrated circuits to higher levels of density and performance. The arguments for and against the adoption of these techniques are presented with illustrations from practical development projects. Some of the key principles behind self-timed operation are reviewed. Design tools to enable complex practical applications to be engineered are considered. For engineers who wish to find out more a selection of key references is provided.
引用
收藏
页码：261 / 270
页数：10
相关论文
共 50 条
  • [41] Self-timed circuits for energy harvesting AC power supplies
    Siebert, J
    Collier, J
    Amirtharajah, R
    ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2005, : 315 - 318
  • [42] The Development of Basic Logic Flement for Strictly Self-timed FPGA
    Kamenskih, Anton N.
    Tyurin, Sergey F.
    2015 INTERNATIONAL CONFERENCE ON INFORMATION AND DIGITAL TECHNOLOGIES (IDT), 2015, : 128 - 131
  • [43] ECL LOGIC-CIRCUITS
    BYERS, TJ
    RADIO-ELECTRONICS, 1983, 54 (09): : 53 - 56
  • [44] Improving smart card security using self-timed circuits
    Moore, S
    Anderson, R
    Cunningham, P
    Mullins, R
    Taylor, G
    ASYNC: EIGHTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2002, : 211 - 218
  • [45] On digit-recurrence division algorithms for self-timed circuits
    Boullis, N
    Tisserand, A
    ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS XI, 2001, 4474 : 115 - 125
  • [46] Improving SRAM Test Quality by Leveraging Self-timed Circuits
    Kinseher, Josef
    Zordan, Leonardo B.
    Polian, Ilia
    Leininger, Andreas
    PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 984 - 989
  • [47] The Synthesis Technique of Fault-Tolerant Self-Timed Circuits
    Kamenskih, Anton N.
    PROCEEDINGS OF THE 2016 IEEE NORTH WEST RUSSIA SECTION YOUNG RESEARCHERS IN ELECTRICAL AND ELECTRONIC ENGINEERING CONFERENCE (ELCONRUSNW), 2016, : 572 - 575
  • [48] Failure-Tolerant Synchronous and Self-Timed Circuits Comparison
    Zatsarinny A.A.
    Stepchenkov Y.A.
    Diachenko Y.G.
    Rogdestvenski Y.V.
    Russian Microelectronics, 2022, 51 (08) : 630 - 632
  • [49] Soft digital signal processing using self-timed circuits
    Kuang, WD
    Yuan, JS
    2002 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2002, : 194 - 198
  • [50] Self-timed MOS Current Mode Logic for digital applications
    Anis, MH
    Elmasry, MI
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V, PROCEEDINGS, 2002, : 113 - 116
12345