A PIPELINED FFT PROCESSOR FOR FILTER BANK PROCESSING

被引：0
|
作者：
BI, G
机构：
来源：
CA-DSP 89, VOLS 1 AND 2: 1989 INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SIGNAL PROCESSING | 1989年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：520 / 525
页数：6
相关论文
共 50 条
  • [21] An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications
    Chen, Yuan
    Tsao, Yu-Chi
    Lin, Yu-Wei
    Lin, Chin-Hung
    Lee, Chen-Yi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2008, 55 (02) : 146 - 150
  • [22] High Speed FFT Processor Design using Radix-24 Pipelined Architecture
    Badar, Swapnil
    Dandekar, D. R.
    2015 INTERNATIONAL CONFERENCE ON INDUSTRIAL INSTRUMENTATION AND CONTROL (ICIC), 2015, : 1050 - 1055
  • [23] An Efficient Pipelined Feedback Processor for Computing a 1024-Point FFT Using Distributed Logic
    Hung Ngoc Nguyen
    Kim, Cheol-Hong
    Kim, Jong-Myon
    ADVANCES IN COMPUTER COMMUNICATION AND COMPUTATIONAL SCIENCES, VOL 1, 2019, 759 : 245 - 256
  • [24] FFT filter bank-based CFAR detection schemes
    Inkol, Robert
    Wang, Sichun
    Rajan, Sreeraman
    2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 2007, : 350 - 353
  • [25] Dynamically Reconfigurable FFT Processor for Flexible OFDM Baseband Processing
    Ferreira, Mario Lopes
    Barahimi, Amin
    Ferreira, Joao Canas
    2016 11TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA (DTIS), 2016,
  • [26] Analysis and Design of Low Power Radix-4 FFT Processor using Pipelined Architecture
    Sophy, P. Augusta
    Srinivasan, R.
    Raja, J.
    Avinash, M.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMPUTING AND COMMUNICATIONS TECHNOLOGIES (ICCCT 15), 2015, : 227 - 232
  • [27] A Two-Dimensional FFT Precoded Filter Bank Scheme
    Pereira Junior, Rogerio
    Faria da Rocha, Carlos Aurelio
    Chang, Bruno S.
    Le Ruyet, Didier
    IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, 2023, 22 (11) : 8366 - 8377
  • [28] Multiplier less FFT processor architecture for signal and image processing
    Prasanthi, R
    Anuradha, V
    Sahoo, SK
    Shekhar, C
    2005 International Conference on Intelligent Sensing and Information Processing, Proceedings, 2005, : 326 - 330
  • [29] Low power pipelined FFT architecture for Synthetic Aperture Radar signal processing
    Kim, BS
    Kim, LS
    PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 1367 - 1370
  • [30] Pipelined FFT Architectures: A Review
    Singh, Sharad
    Kedia, Jyoti
    2015 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, SIGNALS, COMMUNICATION AND OPTIMIZATION (EESCO), 2015,
12345