A 10-BIT 20-MS/S 3-V SUPPLY CMOS A/D CONVERTER

被引：22

作者：

ITO, M ^{[1
]}

MIKI, T ^{[1
]}

HOSOTANI, S ^{[1
]}

KUMAMOTO, T ^{[1
]}

YAMASHITA, Y ^{[1
]}

KIJIMA, M ^{[1
]}

OKUDA, T ^{[1
]}

OKADA, K ^{[1
]}

机构：

[1] MITSUBISHI ELECTR CORP,ULSI LAB,ITAMI,HYOGO 664,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 12期

关键词：

D O I：

10.1109/4.340427

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named ''twin encoders'' enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 mu m CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation.

引用

页码：1531 / 1536

页数：6

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