ARRAY NETWORKS FOR A PARALLEL ADDER AND ITS CONTROL

被引:0
|
作者
ALEKSAND.I
机构
来源
关键词
D O I
10.1109/PGEC.1967.264581
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:226 / &
相关论文
共 50 条
  • [1] Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits
    Asma Taheri Monfared
    Majid Haghparast
    Kamalika Datta
    International Journal of Theoretical Physics, 2019, 58 : 2184 - 2199
  • [2] Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits
    Monfared, Asma Taheri
    Haghparast, Majid
    Datta, Kamalika
    INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS, 2019, 58 (07) : 2184 - 2199
  • [3] Entropy thresholding and its parallel algorithm on the reconfigurable array of processors with wider bus networks
    Lee, SS
    Horng, SJ
    Tsai, HR
    IEEE TRANSACTIONS ON IMAGE PROCESSING, 1999, 8 (09) : 1229 - 1242
  • [4] FULLY PARALLEL ARITHMETIC ALGORITHM FOR AN N-BIT PARALLEL ADDER AND ITS OPTICAL IMPLEMENTATIONS
    LIN, SM
    KUMAZAWA, I
    OPTICS COMMUNICATIONS, 1995, 114 (5-6) : 481 - 490
  • [5] A fully redundant decimal adder and its application in parallel decimal multipliers
    Gorgin, Saeid
    Jaberipur, Ghassem
    MICROELECTRONICS JOURNAL, 2009, 40 (10) : 1471 - 1481
  • [6] An Integrated Nanophotonic Parallel Adder
    Ishihara, Tohru
    Shinya, Akihiko
    Inoue, Koji
    Nozaki, Kengo
    Notomi, Masaya
    ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2018, 14 (02)
  • [7] Parallel prefix adder design
    Beaumont-Smith, A
    Lim, CC
    ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 2001, : 218 - 225
  • [8] DESIGN FOR A PARALLEL BINARY ADDER
    EARNSHAW, JB
    FENWICK, PM
    ELECTRONIC ENGINEERING, 1966, 38 (466): : 794 - &
  • [9] Exploring the Use of Parallel Prefix Adder Topologies into Approximate Adder Circuits
    Macedo, Morgana
    Soares, Leonardo
    Silveira, Bianca
    Diniz, Claudio M.
    da Costa, Eduardo A. C.
    2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 298 - 301
  • [10] Design of 2-Bit Parallel Asynchronous Self-timed Adder and 2-Bit Parallel Adder Using Radix Adder
    Kumar, Kuleen
    Sharma, Tripti
    INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND APPLICATIONS, ICICA 2016, 2018, 632 : 197 - 205