A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance (Ron,sp) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (Wch) and has the effect of modulating current distribution, resulting in lower Ron,sp and higher transconductance (gm). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (Nd-opt) and further reducing the Ron,sp. Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage (BV). Meanwhile, gate-drain charge (QGD) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the Nd-opt. The highly doped N-drift region provides a low-resistance path for the current, which also further reduces Ron,sp. Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the Ron,sp and QGD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.