Triple Metal Extended Source Double Gate Vertical TFET with Boosted DC and Analog/RF Performance for Low Power Applications

A vertical tunnel FET with triple metal and stacked hetero gate dielectric oxide is proposed. In the structure, the gate imbricates the source. Amid the source section and the gate oxide, there is a thin layer of silicon channel. The channel of the proposed structure is perpendicular which increases the probability of a point and line BTBT at the source-channel intersection. In the proposed structure, the metal gate is split into three segments, with the middle section having a higher work function than the other two metal gate sections. An in-channel potential barrier is created by the dissimilarity in work function and bandgap amid the source-channel and drain-channel interfaces, which regulates the tunneling of electrons and ambipolar current. The hetero gate dielectric oxide helps in improving the DC characteristics (ON-state current and OFF-state current) of the device. The simulation results of the TCAD Sentaurus tool are used to investigate the proposed vertical TFET. The proposed work outperforms the Conventional lateral triple metal TFET in terms of elevated ON-state current (incremented by 1.8 × 102 times) and transconductance (incremented by 1.9 × 102 times), less Subthreshold Slope (decremented by 27 mV/decade), and improved ION/IOFF ratio (incremented by 1.2 × 102 times). The proposed device’s analog/RF behaviour has been evaluated and contrasted with Conventional lateral triple metal TFET; the proposed device surpasses it. The improvement in the RF constraints of the proposed device is as follows: fT, GBP, and TFP are incremented by 1.01 × 102, 2.75 × 102, and 2.12 × 102 times, respectively, and τ is reduced by 1 × 102 times.