An efficient stochastic computing based deep neural network accelerator with optimized activation functions

Recently, Deep Neural Networks (DNNs) have played a major role in revolutionizing Artificial Intelligence (AI). These methods have made unprecedented progress in several recognition and detection tasks, achieving accuracy close to, or even better, than human perception. However, their complex architectures requires high computational resources, restricting their usage in embedded devices due to limited area and power. This paper considers Stochastic Computing (SC) as a novel computing paradigm to provide significantly low hardware footprint with high scalability. SC operates on random bit-streams where the signal value is encoded by the probability of a bit in the bit-stream being one. By this representation, SC allows the implementation of basic arithmetic operations including addition and multiplication with simple logic. Hence, SC have potential to implement parallel and scalable DNNs with reduced hardware footprint. A modified SC neuron architecture is proposed for training and implementation of DNNs. Our experimental results show improved classification accuracy on the MNIST dataset by 9.47% compared to the conventional binary computing approach. © 2021, Bharati Vidyapeeth's Institute of Computer Applications and Management.