DTMOS based four-quadrant multiplier/divider with voltage difference transconductance amplifier

In recent years, all portable gadgets must operate at low power in order to increase battery life, increase dependability, and lower the expense of heat dissipation. The four-quadrant multipliers are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. This research proposes a four-quadrant multiplier/divider circuit with Voltage Difference Transconductance Amplifier (VDTA) as the active element. Due to its low power supply and usage of electricity, the suggested four quadrant multiplier/divider circuit is designed with the help of Dynamic Threshold Metal Oxide Semiconductor (DTMOS). Moreover, the proposed design employs a single VDTA as an active element to operate the circuit in a four-quadrant mode for multiplication and division operations. Power usage of the whole circuit is minimized by choosing the voltage supply of 0.2 V. The suggested circuit is created utilizing the Cadence virtuoso GPDK 90 nm technology. Different kinds of performance analyses are estimated to show the effectiveness of the suggested circuit in which the proposed design consumes 0.144 μW\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\mu W$$\end{document} as the usage of electricity value. Also, the suggested circuit has 1.7% total harmonic distortion (THD), which is considerably lesser than the existing designs. The bandwidth is 24.54 MHz, and the intermodulation products of the output signal have been calculated. Monte Carlo and THD simulations have been performed in a way that confirms the robustness of the circuit against the technological spread.