Estimation of BIST Resources During High-Level Synthesis

被引:0
|
作者
Ishwar Parulkar
Sandeep K. Gupta
Melvin A. Breuer
机构
[1] Sun Microsystems,Department of Electrical Engineering—Systems
[2] Inc.,undefined
[3] University of Southern California,undefined
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关键词
built-in self-test; high-level synthesis; estimation;
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学科分类号
摘要
Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal solutions. In this paper we present lower bounds on the number of test resources (i.e., registers that generate pseudo-random test patterns and/or compress test responses) required to test a synthesized data path using built-in self-test (BIST). The bounds on different types of test resources are proved to be individually achievable and experiments show that in most cases the bounds can be achieved simultaneously and with minimum number of functional registers. Efficient ways of computing the lower bounds are developed. The estimations are performed on scheduled data flow graphs with a given module assignment and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of BIST resources to test itself.
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页码:221 / 237
页数:16
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