A comparative simulation study on the power–performance of multi-core architecture

被引:0
|
作者
Vijayalakshmi Saravanan
Alagan Anpalagan
D. P. Kothari
Isaac Woungang
Mohammad S. Obaidat
机构
[1] Ryerson University,WINCORE Lab
[2] I.I.T.,undefined
[3] Monmouth University,undefined
来源
关键词
Multi-core processors; Multi-threading; power–performance; Simulation study;
D O I
暂无
中图分类号
学科分类号
摘要
Nowadays, multi-core processor is the main technology used in desktop PCs, laptop computers and mobile hardware platforms. As the number of cores on a chip keeps increasing, it adds up the complexity and impacts more on both power and performance of a processor. In multi-processors, the number of cores and various parameters, such as issue-width, number of instructions and execution time, are key design factors to balance the amount of thread-level parallelism and instruction-level parallelism. In this paper, we perform a comprehensive simulation study that aims to find the optimum number of processor cores in desktop/laptop computing processor models with shallow pipeline depth. This paper also explores the trade-off between the number of cores and different parameters used in multi-processors in terms of power–performance gains and analyzes the impact of 3D stacking on the design of simultaneous multi-threading and chip multiprocessing. Our analysis shows that the optimum number of cores varies with different classes of workloads, namely: SPEC2000, SPEC2006 and MiBench. Simulation study is presented using architectures with shorter pipeline depth, showing that (1) the optimum number of cores for power–performance is 8, (2) the optimum number of threads in the range [2, 4], and (3) for beyond 32 cores, multi-core processors are no longer efficient in terms of performance benefits and overall power consumption.
引用
收藏
页码:465 / 487
页数:22
相关论文
共 50 条
  • [31] Bahurupi: A Polymorphic Heterogeneous Multi-Core Architecture
    Pricopi, Mihai
    Mitra, Tulika
    ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2012, 8 (04)
  • [32] Adjust ELF Format for Multi-core Architecture
    Hu, Wei
    Chen, Tianzhou
    Zhang, Nan
    Ma, Jijun
    ICECT: 2009 INTERNATIONAL CONFERENCE ON ELECTRONIC COMPUTER TECHNOLOGY, PROCEEDINGS, 2009, : 388 - +
  • [33] An Effective Approach for Multicast on Multi-core Architecture
    Wang, Yuxin
    Yuan, Liye
    Guo, He
    Hui, Xinzhong
    Yang, Yuansheng
    2009 INTERNATIONAL CONFERENCE ON SCALABLE COMPUTING AND COMMUNICATIONS & EIGHTH INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTING, 2009, : 37 - 41
  • [34] A multi-core security architecture based on EFI
    Zhang, Xizhe
    Xie, Yong
    Lai, Xuejia
    Zhang, Shensheng
    Deng, Zijian
    ON THE MOVE TO MEANINGFUL INTERNET SYSTEMS 2007: COOPIS, DOA, ODBASE, GADA, AND IS, PT 2, PROCEEDINGS, 2007, 4804 : 1675 - +
  • [35] Architecture Aware Programming on Multi-Core Systems
    Pimple, M. R.
    Sathe, S. R.
    INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 2011, 2 (06) : 105 - 111
  • [36] Performance prediction and analysis of multi-core cluster systems by parallel simulation
    Xu, Chuan-Fu
    Che, Yong-Gang
    Wang, Zheng-Hua
    Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, 2010, 32 (05): : 62 - 68
  • [37] High-Performance Parallel Fault Simulation for Multi-Core Systems
    Karami, Masoomeh
    Haghbayan, Mohammad-hashem
    Ebrahimi, Masoumeh
    Nejatollahi, Hamid
    Tenhunen, Hannu
    Plosila, Juha
    2021 29TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING (PDP 2021), 2021, : 207 - 211
  • [38] A Multi-core architecture for a hybrid information system
    Hamid, Norhazlina
    Chang, Victor
    Walters, Robert John
    Wills, Gary Brian
    COMPUTERS & ELECTRICAL ENGINEERING, 2018, 69 : 852 - 864
  • [39] A Case Study for Fault Tolerance Oriented Programming in Multi-core Architecture
    Yang, Lu
    Cui, Zhanqi
    Li, Xuandong
    HPCC: 2009 11TH IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2009, : 630 - +
  • [40] Simulation and Performance Analysis of Multi-core Thread Scheduling and Migration Algorithms
    Sibai, Fadi N.
    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMPLEX, INTELLIGENT AND SOFTWARE INTENSIVE SYSTEMS (CISIS 2010), 2010, : 895 - 900