A survey of circuit-level soft error mitigation methodologies

被引：0
|
作者：
Selahattin Sayil
机构：
[1] Lamar University,Electrical Engineering
来源：
Analog Integrated Circuits and Signal Processing | 2019年 / 99卷
关键词：
Single event transients; Combinational logic; Soft error mitigation; Radiation hardening by design;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Soft errors created due to propagation of single event transients are a significant reliability challenge in modern VLSI. With advances in CMOS technology scaling, circuits become increasingly more sensitive to transient pulses caused by energetic particles. This work reviews some popular circuit level SET mitigation techniques developed for combinational logic and compares them with respect to area, power and delay overheads.
引用
收藏
页码：63 / 70
页数：7
相关论文
共 50 条
  • [1] A survey of circuit-level soft error mitigation methodologies
    Sayil, Selahattin
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 99 (01) : 63 - 70
  • [2] Low cost circuit-level soft error mitigation techniques for combinational logic
    Rajaei, R.
    Tabandeh, M.
    Fazeli, M.
    SCIENTIA IRANICA, 2015, 22 (06) : 2401 - 2414
  • [3] Circuit-level modeling of soft errors in integrated circuits
    Walstra, SV
    Dai, CH
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (03) : 358 - 364
  • [4] Circuit-Level Soft Error Rate Evaluation Approach Considering Single-Event Multiple Transient
    Zhang, Xiaoyu
    Liang, Bin
    Song, Ruiqiang
    2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
  • [5] Physical Design Methodologies for Soft Error Mitigation Using Redundancy
    Ramamurthy, Chandarasekaran
    Chellappa, Srivatsan
    Clark, Lawrence T.
    2015 15TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS), 2015,
  • [6] Quantum error correction with an Ising machine under circuit-level noise
    Fujisaki, Jun
    Maruyama, Kazunori
    Oshima, Hirotaka
    Sato, Shintaro
    Sakashita, Tatsuya
    Takeuchi, Yusaku
    Fujii, Keisuke
    PHYSICAL REVIEW RESEARCH, 2023, 5 (04):
  • [7] Exploiting Low Power Circuit Topologies for Soft Error Mitigation
    Mahatme, N. N.
    Chatterjee, I.
    Jagannathan, S.
    Gaspard, N.
    Assis, T.
    Wen, S. -J.
    Wong, R.
    Bhuva, B. L.
    2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
  • [8] Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates
    Zimpeck, Alexandra L.
    Artola, Laurent
    Hubert, Guillaume
    Meinhardt, Cristina
    Kastensmidt, Fernanda L.
    Reis, Ricardo
    2019 19TH EUROPEAN CONFERENCE ON RADIATION AND ITS EFFECTS ON COMPONENTS AND SYSTEMS (RADECS), 2022, : 205 - 210
  • [9] Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs
    Zimpeck, Alexandra L.
    Meinhardt, Cristina
    Artola, Laurent
    Hubert, Guillaume
    Kastensmidt, Fernanda L.
    Reis, Ricardo
    2019 IFIP/IEEE 27TH INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2019, : 240 - 241
  • [10] ELECTROMIGRATION FAILURE OF CIRCUIT-LEVEL INTERCONNECTIONS
    SANCHEZ, JE
    MORRIS, JW
    LLOYD, JR
    JOM-JOURNAL OF THE MINERALS METALS & MATERIALS SOCIETY, 1990, 42 (09): : 41 - 45
12345