Defect-tolerant nanoelectronic pattern classifiers

被引:45
|
作者
Lee, Jung Hoon [1 ]
Likharev, Konstantin K. [1 ]
机构
[1] SUNY Stony Brook, Stony Brook, NY 11794 USA
关键词
nanoelectronics; nanowires; CMOS; CMOL; hybrid circuits; neuromorphic networks; pattern classification; training; learning; defect tolerance;
D O I
10.1002/cta.410
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Mixed-signal neuromorphic networks ('CrossNets'), based on hybrid CMOS/nanodevice circuits, may provide unprecedented performance for important pattern classification tasks. The synaptic weights necessary for such tasks may be imported from an external 'precursor' network with either continuous or discrete synaptic weights (in the former case, with the quantization-'clipping'-due to the binary character of the elementary synaptic nanodevices-latching switches.) Alternatively, the weights may be adjusted 'in situ' (inside the CrossNet) using a pseudo-stochastic method, or set-up using a mixed-mode method partly employing external circuitry. Our calculations have shown that CrossNet pattern classifiers, using any of these synaptic weight adjustment methods, may be remarkably resilient. For example, in a CrossNet with synapses in the form of two small square arrays with 4 x 4 nanodevices each, the resulting weight discreteness may have a virtually negligible effect on the classification fidelity, while the fraction of defective devices which affects the performance substantially ranges from similar to 20% to as high as 90% (!), depending on the training method. Copyright (C) 2007 John Wiley & Sons, Ltd.
引用
收藏
页码:239 / 264
页数:26
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