Low-temperature high-density chip-stack interconnection using compliant bump

被引：8

作者：

Watanabe, Naoya ^{[1
]}

Asano, Tanemasa ^{[2
]}

机构：

[1] Kumamoto Technol & Ind Fdn, Appl Elect Res Ctr, 2081-10 Tabaru, Kumamoto 8612202, Japan

[2] Kyushu Univ, Fac Informat Sci & Elect Engn, Nishi Ku, Fukuoka 8190395, Japan

来源：

57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/ECTC.2007.373861

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate low-temperature high-density chip-stack interconnection using compliant bump. Low temperature chip stacking was carried out by two methods; (1) plasma cleaning of compliant bumps, (2) mechanical caulking using compliant bump and doughnut-shaped electrode. The latter method is very effective in realizing chip stacking even at room temperature.

引用

页码：622 / +

页数：2

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