共 50 条
- [1] Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis PROCEEDINGS OF THE 2021 TWENTY SECOND INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2021), 2021, : 24 - 30
- [2] Test generation for double stuck-at faults 10TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2001, : 71 - 75
- [3] Fast test generation for circuits with RTL and gate-level views INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1068 - 1077
- [4] Functional Test Generation for Hard to Detect Stuck-At Faults using RTL Model Checking 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
- [5] Representing Gate-Level SET Faults by Multiple SEU Faults at RTL 2020 26TH IEEE INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2020), 2020,
- [6] Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults Integration, 2022, 83 : 24 - 32
- [7] Test Pattern Generation for Multiple Stuck-at Faults Not Covered by Test Patterns for Single Faults 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 2465 - 2468
- [8] Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits Journal of Electronic Testing, 1997, 11 : 227 - 245
- [9] Distributed test pattern generation for stuck-at faults in sequential circuits JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1997, 11 (03): : 227 - 245
- [10] Distributed test pattern generation for stuck-at faults in sequential circuits J Electron Test Theory Appl JETTA, 3 (227-245):