Subthreshold 1-bit full adder cells in sub-100 nm technologies

被引：4

作者：

Moalemi, Vahid ^{[1
]}

Afzali-Kushu, Ali ^{[1
]}

机构：

[1] Univ Tehran, Sch Elect & Comp Engn, Tehran 14174, Iran

来源：

IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES | 2007年

关键词：

D O I：

10.1109/ISVLSI.2007.93

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, subthreshold 1-bitfull adder cells in sub100 nm technologies are investigated. The analysis is performed using fourteen different full adder cells operating in subthreshold region by decomposing them into smaller blocks. Both individual blocks and the complete full adder cells are simulated. The study, which is carried out for 65nm and 90nm standard CMOS technologies, includes power, delay, and power delay product as functions of supply voltage, frequency, size, and technology. In addition, for both technologies, the minimum required supply voltage for different circuits, are determined.

引用

页码：514 / +

页数：2

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