Power Efficient LCR Dual Keeper Domino Logic Circuit

In VLSI circuit design researchers are concerned about reduction of the power. Domino logic circuit fulfills this goal. This paper proposes a low power domino logic circuit in which the evaluation network has been modified for a significant reduction in power. In the proposed work, a current minor circuit and an additional discharge path are introduced. The current mirror circuit replicates and tracks leakage current while an additional discharge path facilitates dynamic node faster discharging during the evaluation phase. The simulations are performed using CADENCE virtuoso EDA tool with the help of UMC 45 nm, 90 nm and 180 nm technology library for 2,4 and 8 inputs AND and OR gates. The proposed circuit consumes lesser power as compared to some existing circuits. The proposed circuit consumes 38.92% and 17.90% less power as compared to some existing domino logic circuits for 8-bit input OR gate in 180nm technology. The power is reduced by 68.68%, 17.85% and 87.65%, 29.69% respectively in 90 nm and 45 nm technology as compared with other existing circuits.