Design of a 65-69 GHz 1000:1 FMCW PLL in 65nm CMOS Technology

被引:0
|
作者
Nasrollahpour, Mehdi [1 ,2 ]
Agrawal, Priyanka [1 ,2 ]
Sreekumar, Rahul [1 ,2 ]
Yen, Chi-Hsien [1 ,2 ]
Aldacher, Muhammad [1 ,2 ]
Ye, Song [1 ,3 ]
Hamedi-Hagh, Sotoudeh [1 ,2 ]
机构
[1] San Jose State Univ, RFIC Lab, San Jose, CA 95192 USA
[2] San Jose State Univ, San Jose, CA 95192 USA
[3] Chengdu Univ Informat Technol, 24 Block 1 Xuefu Rd, Chengdu 610225, Sichuan, Peoples R China
关键词
radar; FMCW; PLL; source follower; phase noise; PHASE-LOCKED LOOP; FREQUENCY-SYNTHESIZER;
D O I
10.1109/wmcas.2019.8732550
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Frequency Modulated Continuous Wave (FMCW) radar systems have found extensive applications in the field of automotive radar and imaging. A fully integrated 65-69 GHz FMCW characteristic frequency synthesizer is presented in this work. The proposed phase locked-loop (PLL) features a 1000:1 frequency division ratio and a novel idea for a source follower buffer based LC voltage controlled oscillator. To achieve a highly linear transfer characteristic, an optimal frequency division topology is implemented. The overall system achieves a range resolution of 7.5 cm and exhibits a closed loop phase noise of -98.5 dBc/Hz at a 1MHz offset frequency. An initial locking period of 1.67 mu s is achieved by the system while exhibiting a linear VCO output characteristic over the desired frequency range.
引用
收藏
页数:5
相关论文
共 50 条
  • [41] A Low-Loss 220GHz-325GHz Marchand Balun in 65nm CMOS Technology
    Tian, Anyi
    Liu, Chenxin
    Sakai, Hiroyuki
    Kunihiro, Kazuaki
    Shirane, Atsushi
    Okada, Kenichi
    2024 54TH EUROPEAN MICROWAVE CONFERENCE, EUMC 2024, 2024, : 1026 - 1029
  • [42] Design of 60GHz Broadband LNA for 5G Cellular using 65nm CMOS Technology
    Pournamy, S.
    Kumar, Navin
    2017 7TH INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS AND NETWORK TECHNOLOGIES (CSNT), 2017, : 320 - 324
  • [43] Co-Design and Optimization of a 320 GHz On-Chip Antenna for THz detection in 65nm CMOS Technology
    Quarta, Gabriele
    Perenzoni, Matteo
    D'Amico, Stefano
    2021 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT), 2021,
  • [44] A Spatial-LDI Δ-Σ LNA Design in 65nm CMOS
    Silva, Nimasha
    Mandal, Soumyajit
    Belostotski, Leonid
    Madanayake, Arjuna
    2024 INTERNATIONAL APPLIED COMPUTATIONAL ELECTROMAGNETICS SOCIETY SYMPOSIUM, ACES 2024, 2024,
  • [45] Design of 6-bit 28GHz Phase Shifter in 65nm CMOS
    Park, Jeehoon
    Kong, Sunwoo
    Jang, Seunghyun
    Lee, Hui Dong
    Kim, Kwang-Seon
    Lee, Kwang Chun
    2018 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS (APMC), 2018, : 1513 - 1515
  • [46] Design and Analysis of Wide Tuning Range Ring VCO in 65nm CMOS Technology
    Askari S.
    Saneei M.
    Salem S.
    Radioelectronics and Communications Systems, 2019, 62 (5) : 232 - 240
  • [47] Rigorous extraction of process variations for 65nm CMOS design
    Zhao, Wei
    Cao, Yu
    Liu, Frank
    Agarwal, Kanak
    Acharyya, Dhruva
    Nassif, Sani
    Nowka, Kevin
    ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, : 89 - +
  • [48] A 65nm CMOS Ka-band AGC Design
    Liu, Zhang-fa
    Wu, Jia-qian
    2ND INTERNATIONAL CONFERENCE ON MODELING, SIMULATION AND OPTIMIZATION TECHNOLOGIES AND APPLICATIONS (MSOTA 2018), 2018, : 187 - 193
  • [49] A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS
    Abedi, Razieh
    Kananizadeh, Rouzbeh
    Esmaili, Amir
    Momeni, Omeed
    Heydari, Payam
    2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
  • [50] A 171GHz harmonic-mode PLL with-14.2dBm output power in 65nm CMOS
    Jain, Sanjeev
    Belostotski, Leonid
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 98 (03) : 643 - 649