Design of a 65-69 GHz 1000:1 FMCW PLL in 65nm CMOS Technology

被引:0
|
作者
Nasrollahpour, Mehdi [1 ,2 ]
Agrawal, Priyanka [1 ,2 ]
Sreekumar, Rahul [1 ,2 ]
Yen, Chi-Hsien [1 ,2 ]
Aldacher, Muhammad [1 ,2 ]
Ye, Song [1 ,3 ]
Hamedi-Hagh, Sotoudeh [1 ,2 ]
机构
[1] San Jose State Univ, RFIC Lab, San Jose, CA 95192 USA
[2] San Jose State Univ, San Jose, CA 95192 USA
[3] Chengdu Univ Informat Technol, 24 Block 1 Xuefu Rd, Chengdu 610225, Sichuan, Peoples R China
关键词
radar; FMCW; PLL; source follower; phase noise; PHASE-LOCKED LOOP; FREQUENCY-SYNTHESIZER;
D O I
10.1109/wmcas.2019.8732550
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Frequency Modulated Continuous Wave (FMCW) radar systems have found extensive applications in the field of automotive radar and imaging. A fully integrated 65-69 GHz FMCW characteristic frequency synthesizer is presented in this work. The proposed phase locked-loop (PLL) features a 1000:1 frequency division ratio and a novel idea for a source follower buffer based LC voltage controlled oscillator. To achieve a highly linear transfer characteristic, an optimal frequency division topology is implemented. The overall system achieves a range resolution of 7.5 cm and exhibits a closed loop phase noise of -98.5 dBc/Hz at a 1MHz offset frequency. An initial locking period of 1.67 mu s is achieved by the system while exhibiting a linear VCO output characteristic over the desired frequency range.
引用
收藏
页数:5
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