Vertical Arbitration-Free 3-D NoCs

The vertical interlayer communication channel plays a critical role in defining the performance of a 3-D networkon-chip (NoC). In this paper, an arbitration-free design for the shared vertical channels is proposed. The proposed vertical arbitration-free 3-D NoC is compared with other 3-D NoC architectures using traditional synthetic traffic patterns and Rentian traffic emulating applications for chip multiprocessors. The results of the analysis show comparable performance in throughput, energy, and latency compared to a symmetric 3-D NoC with savings up to approximate to 20% in area. The proposed NoC is superior in performance to a 3-D NoC utilizing vertical arbitration with a similar area footprint.