Architecture-Aware Design of a Decimation Filter Based on a Dual Wordlength Multiply-Accumulate Unit

被引：0
|
作者：
Lindahl, Erik [1 ]
Gustafsson, Oscar [1 ]
机构：
[1] Linkoping Univ, Dept Elect Engn, SE-58183 Linkoping, Sweden
来源：
2008 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1-4 | 2008年
关键词：
D O I：
10.1109/ACSSC.2008.5074758
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In this work we present the design and implementation of a decimation filter for an audio range AE-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.
引用
收藏
页码：1897 / 1901
页数：5
相关论文
共 30 条
  • [1] Architecture and implementation of a vector/SIMD multiply-accumulate unit
    Danysh, A
    Tan, D
    IEEE TRANSACTIONS ON COMPUTERS, 2005, 54 (03) : 284 - 293
  • [2] DESIGN OF A DELAY-INSENSITIVE MULTIPLY-ACCUMULATE UNIT
    NIELSEN, CD
    MARTIN, AJ
    INTEGRATION-THE VLSI JOURNAL, 1993, 15 (03) : 291 - 311
  • [3] Design of High Performance Multiply-Accumulate Computation Unit
    Ahish, S.
    Kumar, Y. B. N.
    Sharma, Dheeraj
    Vasantha, M. H.
    2015 IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC), 2015, : 915 - 918
  • [4] New design of an RSFQ parallel multiply-accumulate unit
    Kataeva, Irina
    Engseth, Henrik
    Kidiyarova-Shevchenko, Anna
    SUPERCONDUCTOR SCIENCE & TECHNOLOGY, 2006, 19 (05): : S381 - S386
  • [5] Design and Performance Analysis of Multiply-Accumulate (MAC) Unit
    SaiKumar, Maroju
    Kumar, D. Ashok
    Samundiswary, P.
    2014 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT-2014), 2014, : 1084 - 1089
  • [6] FPGA IMPLEMENTATION OF LOWPASS FIR FILTER USING SINGLE MULTIPLY-ACCUMULATE UNIT WITH DUAL-PORT RAM
    Aljumaili, Amer kais
    Hassan, Raaed f.
    Hamza, Ekhlas k.
    Humaidi, Amjad j.
    JOURNAL OF ENGINEERING SCIENCE AND TECHNOLOGY, 2025, 20 (01): : 345 - 361
  • [7] Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications
    Tatas, K.
    Koutroumpezis, G.
    Soudris, D.
    Thanailakis, A.
    INTEGRATION-THE VLSI JOURNAL, 2007, 40 (02) : 74 - 93
  • [8] A pipelined multiply-accumulate unit design for energy recovery DSP systems
    Suvakovic, D
    Salama, CAT
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL I: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 16 - 19
  • [9] Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems
    Cini, Ugur
    Kocyigit, Gokhan
    ELEKTRONIKA IR ELEKTROTECHNIKA, 2017, 23 (02) : 36 - 39
  • [10] A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units
    Lyakhov, Pavel
    Valueva, Maria
    Valuev, Georgii
    Nagornov, Nikolai
    APPLIED SCIENCES-BASEL, 2020, 10 (24): : 1 - 11
123