Architecture-Aware Design of a Decimation Filter Based on a Dual Wordlength Multiply-Accumulate Unit

被引：0
|
作者：
Lindahl, Erik [1 ]
Gustafsson, Oscar [1 ]
机构：
[1] Linkoping Univ, Dept Elect Engn, SE-58183 Linkoping, Sweden
来源：
2008 42ND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1-4 | 2008年
关键词：
D O I：
10.1109/ACSSC.2008.5074758
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
In this work we present the design and implementation of a decimation filter for an audio range AE-modulator. The architecture is based on a dual wordlength multiply-accumulate (MAC) unit to handle the reduced wordlength of the input. Each stage is composed of FIR filters which are mapped to the MAC unit. The design trade-offs and decisions for co-design of architecture and filters are discussed.
引用
收藏
页码：1897 / 1901
页数：5
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