Analysis of a novel self-aligned elevated source drain metal-oxide-semiconductor field-effect transistor with reduced gate-induced drain leakage current and high driving capability

A new self-aligned elevated source drain (E-S/D) metal-oxide-semiconductor field-effect transistor (MOS FET) structure which can effectively reduce the gate-induced drain leakage (GIDL) current without sacrificing the driving capability is proposed and analyzed. Proposed E-S/D structure is characterized by sidewall spacer width and recessed-channel depth which are determined by dry etching process. Elevation of the Source/Drain extension region is realized so that the low-activation effect caused by low-energy ion implantation can be avoided. The GIDL current in the proposed E-S/D structure is reduced as the region with the peak electric field is shifted toward the drain side.