Performance Analysis of Impact of Source/Drain Doping Gradients Well as Roll-Off Widths on Gate Induced Drain Leakage of Double Gate Metal Oxide Semiconductor Field Effect Transistor

被引：4

作者：

Kumar, Parveen ^{[1
]}

Gill, Sandeep Singh ^{[1
]}

机构：

[1] Guru Nanak Dev Engn Coll, Dept Elect & Commun Engn, Ludhiana 141006, Punjab, India

来源：

JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS | 2018年 / 13卷 / 11期

关键词：

DGMOSFET; Short Channel Effects (SCEs) and Gate-Induced-Drain-Leakage (GIDL); Overlap/Underlap Channel; Source/Drain Doping Gradients (d); Source/Drain Roll-Off Widths (ms); MODEL;

D O I：

10.1166/jno.2018.2426

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper investigates the importance of overlap/underlap design of channel in Double Gate (DG) MOSFETs to improve Short Channel Effects (SCEs) and Gate Induced Drain Leakage (GIDL). A systematic study of GIDL is a very important analysis in DGMOSFET. Gate underlap architecture is useful to reduce the GIDL and improve the SCEs in DGMOSFET structure. The results show that steeper Source/Drain (S/D) doping gradients along with wider S/D roll-off width will be required for the device. In order to enhance short channel immunity, the ratio of S/D roll-off width to lateral straggle should be high for a wide range of SID doping gradients. This research provides innovative solution for realizing opportunity of very low power devices as well as circuits through underlap DGMOSFETs.

引用

页码：1705 / 1710

页数：6

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