Hardware implementation of discrete stochastic arithmetic

被引：0
|
作者：
Avot-Chotin, R [1 ]
Mehrez, H [1 ]
机构：
[1] UPMC, LIP6 ASIM Lab, F-75252 Paris 05, France
来源：
NUMERICAL ALGORITHMS | 2004年 / 37卷 / 1-4期
关键词：
stochastic arithmetic; accuracy control; floating-point arithmetic; arithmetic hardware; CESTAC method;
D O I：
10.1023/B:NUMA.0000049455.07441.ee
中图分类号：
O29 [应用数学];
学科分类号：
070104 ;
摘要：
In this paper we present a hardware implementation of the Discrete Stochastic Arithmetic (DSA) which is based on CESTAC (Controle et Estimation STochastique des Arrondis de Calculs), a method of controlling round-off errors in floating-point scientific computations. Real-time software implementation of this method suffers from computation bottlenecks. This paper gives a hardware alternative that would significantly accelerate the computation. The proposed architecture is based on a Stochastic Floating-Point Unit (SFPU) which performs discrete stochastic operations. This SFPU has been integrated in a coprocessor, used in a complete System on Chip (SoC).
引用
收藏
页码：21 / 33
页数：13
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