Parallelization of Discrete Stochastic Arithmetic on multicore architectures

被引:1
|
作者
Jezequel, F. [1 ]
Lamotte, J-L [1 ]
Chubach, O. [2 ]
机构
[1] Univ Paris 06, UMR 7606, Lab Informat Paris 6, 4 Pl Jussieu, F-75252 Paris 05, France
[2] Odessa I I Mechnikov Natl Univ, UA-65082 Odessa, Ukraine
关键词
Discrete Stochastic Arithmetic; floating-point arithmetic; multicore processors; numerical validation; round-off errors; COMPUTATION; CADNA;
D O I
10.1109/ITNG.2013.28
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Discrete Stochastic Arithmetic (DSA) estimates round-off error propagation in a program. It is based on a synchronous execution of several instances of the program to control using a random rounding mode. In this paper we show how we can take advantage of multicore processors, which are nowadays widespread, to reduce the cost of DSA in terms of execution time. Several processes execute in parallel different instances of the program and exchange data when necessary. Several strategies are compared for the estimation of the result accuracy and the detection of numerical instabilities. With our parallel implementation, the cost of DSA is reduced by a factor of about 2 compared with the sequential approach. Our parallel implementation of DSA has been used successfully for the numerical validation of a real-life application.
引用
收藏
页码:160 / 166
页数:7
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