Hardware Implementation of Discrete Hirschman Transform Convolution Using Distributed Arithmetic

A fast linear convolution algorithm based on the Discrete Hirschman Transform (DHT) has been developed recently. It performs better than the traditional convolution based on the Discrete Fourier Transform (DFT) in terms of computational complexity. We propose a linear convolution filter implementation using the Distributed Arithmetic (DA) technique for this DHT convolution algorithm. We have realized it in FPGAs to determine its hardware performance. Compared to the traditional DFT convolution filter using the same DA technique, simulation results indicate that our proposed DHT convolution filter has better accuracy. It can also yield more savings in real computations, accesses to memory and latency by more than 23%, 23% and around 25%, respectively.