Timing issues in system-level design

被引:2
|
作者
Dasdan, A [1 ]
Gupta, RK [1 ]
机构
[1] Univ Illinois, Dept Comp Sci, Urbana, IL 61801 USA
关键词
D O I
10.1109/IWV.1998.667136
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present our view of the high-level timing issues in the design and validation of embedded real-time systems. We first define the derivation problem: the problem of deriving internal timing constraints from external timing constraints in an embedded real-time system. We then give a comprehensive classification of timing constraints, discuss the stare of the art on high-level system modeling and on the timing constraint derivation techniques. We finally give some pointers for future research.
引用
收藏
页码:124 / 129
页数:6
相关论文
共 50 条
  • [1] Early Timing Estimation for System-Level Design Using FPGAs
    Andrade, Hugo
    Ghosal, Arkadeb
    Limaye, Rhishikesh
    Malik, Sadia
    Petersen, Newton
    Ravindran, Kaushik
    Trung Tran
    Wang, Guoqiang
    Yang, Guang
    FPGA 12: PROCEEDINGS OF THE 2012 ACM-SIGDA INTERNATIONAL SYMPOSIUM ON FIELD PROGRAMMABLE GATE ARRAYS, 2012, : 271 - 271
  • [2] TIMING VERIFICATION FOR SYSTEM-LEVEL DESIGNS
    CHIANG, M
    BLOOM, M
    VLSI SYSTEMS DESIGN, 1987, 8 (13): : 46 - +
  • [3] SYSTEM-LEVEL DESIGN
    BOURBON, B
    COMPUTER DESIGN, 1990, 29 (23): : 19 - 21
  • [4] Aspects on system-level design
    Plantin, J
    Stoy, E
    PROCEEDINGS OF THE SEVENTH INTERNATIONAL WORKSHOP ON HARDWARE/SOFTWARE CODESIGN (CODES'99), 1999, : 209 - 210
  • [5] Challenges in system-level design
    Wolf, W
    FORMAL METHODS IN COMPUTER-AIDED DESIGN, 2004, 3312 : 1 - 5
  • [6] Challenges in system-level design
    Wolf, W
    FORMAL METHODS IN COMPUTER-AIDED DESIGN, PROCEEDINGS, 2004, 3312 : 1 - 5
  • [7] No wait for system-level design
    IET Electron. Syst. Softw., 2006, 6 (02):
  • [8] Design complexity requires system-level design
    Moretti, G
    EDN, 2005, 50 (05) : 26 - +
  • [9] A general approach to modelling system-level timing constraints
    Jersak, M
    Ziegenbein, D
    Ernst, R
    SYSTEM ON CHIP DESIGN LANGUAGES: EXTENDED PAPERS: BEST OF FDL'01 AND HDLCON'01, 2002, : 275 - 283
  • [10] Transformation of SDL specifications for system-level timing analysis
    Jersak, M
    Richter, K
    Henia, R
    Ernst, R
    Slomka, F
    CODES 2002: PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, 2002, : 121 - 126