共 50 条
- [41] Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2019,
- [43] TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020,
- [44] Failure Analysis of Plastic Packages for Low-Power ICs APPLICATIONS IN ELECTRONICS PERVADING INDUSTRY, ENVIRONMENT AND SOCIETY, APPLEPIES 2016, 2018, 429 : 160 - 166
- [45] Thermal Pathfinding for 3-D ICs IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (07): : 1159 - 1168
- [47] Low-power design NINTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 1996, : 323 - 323
- [48] Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited) 2021 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL INTERCONNECT PATHFINDING (SLIP 2021), 2021, : 17 - 23
- [49] A recursive algorithm for low-power memory partitioning ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 78 - 83
- [50] Recursive algorithm for low-power memory partitioning Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 2000, : 78 - 83