Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning

被引：10

作者：

Jung, Moongon ^{[1
]}

Song, Taigon ^{[2
]}

Peng, Yarui ^{[2
]}

Lim, Sung Kyu ^{[2
]}

机构：

[1] Intel, Intel Labs, Santa Clara, CA 95054 USA

[2] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2017年 / 25卷 / 07期

关键词：

3-D integrated circuits; block folding; low power; physical design methods; ANALYTICAL PLACEMENT;

D O I：

10.1109/TVLSI.2017.2670508

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Low power is considered as the driving force for 3-D ICs, yet there have been few thorough design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided design techniques and design methodologies to reduce power consumption in 3-D IC designs using a commercial grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3-D ICs, four design techniques are explored: 1) 3-D floorplanning; 2) metal layer usage control for intrablock-level routing; 3) dual-Vth design; and 4) functional unit block (FUB) folding. The benefits and challenges of multiple FUB folding are also discussed. Finally, the through-silicon via technology scaling impact on FUB folding and 3-D power benefit is examined. With the aforementioned methods combined, our 2-tier 3-D designs provide up to 52.3% reduced footprint, 27.9% shorter wirelength, 35.4% decreased buffer cell count, and 27.8% power reduction over the 2-D counterpart under the same performance.

引用

页码：2109 / 2117

页数：9