A novel area efficient floating field limiting ring edge termination technique

被引：19
|
作者：
De Souza, MM
Bose, JVSC
Narayanan, EMS
Pease, TJ
Ensell, G
Humphreys, J
机构：
[1] De Montfort Univ, SER Ctr, Emerging Technol Res Ctr, Leicester LE1 9BH, Leics, England
[2] Univ Southampton Highfields, Ctr Microelect, Southampton, Hants, England
来源：
SOLID-STATE ELECTRONICS | 2000年 / 44卷 / 08期
基金：
英国工程与自然科学研究理事会;
关键词：
D O I：
10.1016/S0038-1101(00)00077-0
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a floating ring edge termination structure using minimally sized lightly doped p-rings is proposed. A novel embodiment of the structure involves placement of shallow p(+)-regions offset from the centre of each of the p-well rings to reduce peak electric field at the surface and to reduce sensitivity to oxide interface charges. The structures have been fabricated using an advanced, 2 kV MOS-bipolar process technology. A close match between the simulated and experimental results validates the proposed structure. (C) 2000 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：1381 / 1386
页数：6
相关论文
共 50 条
  • [1] A novel area efficient edge termination technique for planar, MOS controlled power devices
    Bose, JVSC
    De Souza, MM
    Sweet, M
    Spulber, O
    Narayanan, EMS
    PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II, 2000, 3975 : 349 - 352
  • [2] A new edge termination technique to improve voltage blocking capability and reliability of field limiting ring for power devices
    Kim, Yo Han
    Lee, Han Sin
    Kyung, Sin Su
    Kim, Young Mok
    Kang, Ey Goo
    Sung, Man Young
    2008 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2008, : 71 - +
  • [3] Enhancing the robustness of a multiple floating field-limiting ring termination by introducing a buffer layer
    Vanmeerbeek, P.
    Roig, J.
    Bogman, F.
    Moens, P.
    Villamor-Baliarda, A.
    Flores, D.
    2012 24TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2012, : 357 - 360
  • [4] A robust and area-efficient guard ring edge termination technique for 4H-SiC power MOSFETs
    Deng, Xiaochuan
    Guo, Yuanxu
    Dai, Tianxiang
    Li, Chengzhan
    Chen, Ximing
    Chen, Wanjun
    Zhang, Yourun
    Zhang, Bo
    MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2017, 68 : 108 - 113
  • [5] Electric field unbalance for robust floating ring termination
    Villamor-Baliarda, A.
    Vanmeerbeek, P.
    Roig, J.
    Moens, P.
    Flores, D.
    MICROELECTRONICS RELIABILITY, 2011, 51 (9-11) : 1959 - 1963
  • [6] Design methodology and simulation tool for floating ring termination technique
    Stefanov, E
    Charitat, G
    Bailon, L
    SOLID-STATE ELECTRONICS, 1998, 42 (12) : 2251 - 2257
  • [7] A concept of a novel edge termination technique: Junction Termination (RJT)
    Honda, Shigeto
    Fujii, Ryoich
    Kawakami, Tsuyoshi
    Fujioka, Seiji
    Narazaki, Atsushi
    Motonami, Kaoru
    2010 22ND INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2010, : 111 - 114
  • [8] A concise analytical approach for predicting the voltage and edge peak field profiles of the planar junction with a single floating field limiting ring
    He, J
    Zhang, X
    Wang, YY
    INTERNATIONAL JOURNAL OF ELECTRONICS, 2001, 88 (08) : 903 - 914
  • [9] Destruction behavior in high voltage diode with the field limiting ring termination
    Zhang, Lei
    Wang, Cailin
    Song, Yang
    IEICE ELECTRONICS EXPRESS, 2019, 16 (08):
  • [10] A Near Ideal Edge Termination Technique for Ultrahigh-Voltage 4H-SiC Devices with Multi-Zone Gradient Field Limiting Ring
    Deng, Xiaochuan
    Xu, Shaodong
    Zhang, Bo
    Zeng, Lirao
    Li, Chenzhan
    Wu, Jia
    Li, Juntao
    2018 1ST WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS IN ASIA (WIPDA ASIA), 2018, : 144 - +
12345