High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation

被引:10
|
作者
Koshita, Shunsuke [1 ]
Onizawa, Naoya [2 ,3 ]
Abe, Masahide [1 ]
Hanyu, Takahiro [3 ]
Kawamata, Masayuki [1 ]
机构
[1] Tohoku Univ, Grad Sch Engn, Sendai, Miyagi 9808579, Japan
[2] Tohoku Univ, Frontier Res Inst Interdisciplinary Sci, Sendai, Miyagi 9808578, Japan
[3] Tohoku Univ, Res Inst Elect Commun, Sendai, Miyagi 9808577, Japan
来源
关键词
FIR digital filter; stochastic computation; computational accuracy; digital circuit implementation;
D O I
10.1587/transinf.2016LOP0011
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents FIR digital filters based on stochastic/binary hybrid computation with reduced hardware complexity and high computational accuracy. Recently, some attempts have been made to apply stochastic computation to realization of digital filters. Such realization methods lead to significant reduction of hardware complexity over the conventional filter realizations based on binary computation. However, the stochastic digital filters suffer from lower computational accuracy than the digital filters based on binary computation because of the random error fluctuations that are generated in stochastic bit streams, stochastic multipliers, and stochastic adders. This becomes a serious problem in the case of FIR filter realizations compared with the IIR counterparts because FIR filters usually require larger number of multiplications and additions than IIR filters. To improve the computational accuracy, this paper presents a stochastic/binary hybrid realization, where multipliers are realized using stochastic computation but adders are realized using binary computation. In addition, a coefficient-scaling technique is proposed to further improve the computational accuracy of stochastic FIR filters. Furthermore, the transposed structure is applied to the FIR filter realization, leading to reduction of hardware complexity. Evaluation results demonstrate that our method achieves at most 40dB improvement in minimum stopband attenuation compared with the conventional pure stochastic design.
引用
收藏
页码:1592 / 1602
页数:11
相关论文
共 50 条
  • [1] Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation
    Koshita, Shunsuke
    Onizawa, Naoya
    Abe, Masahide
    Hanyu, Takahiro
    Kawamata, Masayuki
    2016 IEEE 46TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2016), 2016, : 223 - 228
  • [2] Novel Structure for Area-Efficient Implementation of FIR Filters
    Lou, Xin
    Meher, Pramod Kumar
    Yu, Yajun
    Ye, Wenbin
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64 (10) : 1212 - 1216
  • [3] A novel implementation scheme for high area-efficient DCT based on signed stochastic computation
    Li, Yan
    Hu, Jianhao
    2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 990 - 993
  • [4] Area-efficient parallel FIR digital filter implementations
    Parker, DA
    Parhi, KK
    INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS 1996, PROCEEDINGS, 1996, : 93 - 111
  • [5] Design of high-speed, low-power, and area-efficient FIR filters
    Liacha, Ahmed
    Oudjida, Abdelkrim K.
    Ferguene, Farid
    Bakiri, Mohammed
    Berrandjia, Mohamed L.
    IET CIRCUITS DEVICES & SYSTEMS, 2018, 12 (01) : 1 - 11
  • [6] Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
    Tsao, Yu-Chi
    Choi, Ken
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2012, 59 (06) : 371 - 375
  • [7] HIGH-ACCURACY STOCHASTIC COMPUTING-BASED FIR FILTER DESIGN
    Ahmed, Kazi J.
    Yuan, Bo
    Lee, Myung J.
    2018 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP), 2018, : 1140 - 1144
  • [8] Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
    Tsao, Yu-Chi
    Choi, Ken
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (02) : 366 - 371
  • [9] An Area-efficient High-accuracy Prediction-based CABAC Decoder Architecture for H.264/AVC
    Kuo, Ming-Yu
    Li, Yao
    Lee, Chen-Yi
    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 1960 - 1963
  • [10] An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach
    Poonnen, Thomas
    Fam, Adly T.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2008, 54 (12) : 1122 - 1128