A CMOS low-power, high-speed, asynchronous comparator for synchronous rectification applications

被引：0
|
作者：
Levy, G [1 ]
Piovaccari, A [1 ]
机构：
[1] Analog Mixed Signal Design Grp, Cadence Design Syst, Columbia, MD 21046 USA
来源：
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel approach for the design of an asynchronous comparator implemented in standard digital CMOS technology for power supply applications is presented. The 1mV-sensitivity comparator is designed for asynchronous event detection, featuring a multi-stage topology for power efficiency and minimum propagation delay. It also contains a mixed-mode offset compensation architecture that allows full compensation in a single cycle. The comparator has been successfully used in the design of a very high frequency, 300mA multi-mode PWM/PSM (Pulse Width Modulation/Pulse Skipping Mode) buck converter. The comparator is able to operate with a supply voltage as low as 2.4V. Operating with a 3.6V supply, under typical operating conditions, the comparator features a 19ns delay consuming 161 mu W.
引用
收藏
页码：541 / 544
页数：4
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