Impact of technology scaling on RF CMOS

被引：6
|
作者：
Hassan, H [1 ]
Anis, M [1 ]
Elmasry, M [1 ]
机构：
[1] Univ Waterloo, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/SOCC.2004.1362363
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Inspired by the huge improvement in the RF properties of CMOS, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of the CMOS; frequency properties,, noise performance, linearity, stability, and non-quasi static effects, is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Using the BSIM4 model it is found that future CANS technologies have high prospects in the RF industry.
引用
收藏
页码：97 / 101
页数：5
相关论文
共 50 条
  • [31] CMOS technology for MS/RF SoC
    Diaz, CH
    2004 IEEE WORKSHOP ON MICROELECTRONIC AND ELECTRON DEVICES, 2004, : 24 - 27
  • [32] CMOS technology adjusts to RF applications
    Kolding, TE
    Mikkelsen, JH
    Larsen, T
    MICROWAVES & RF, 1998, 37 (06) : 79 - +
  • [33] Advanced CMOS Scaling, And FinFET Technology
    Nowak, E. J.
    SIGE, GE, AND RELATED COMPOUNDS 5: MATERIALS, PROCESSING, AND DEVICES, 2012, 50 (09): : 3 - 16
  • [34] Impact of Proton Irradiation on the RF Performance of 65 nm SOI CMOS Technology
    Madan, Anuj
    Phillips, Stanley D.
    Cressler, John D.
    Marshall, Paul W.
    Liang, Qingqing
    Freeman, Greg
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (04) : 1914 - 1919
  • [35] CMOS technology for MS/RF SoC
    Diaz, CH
    Tang, DD
    Sun, J
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (03) : 557 - 566
  • [36] Impact of technology scaling on bridging fault detections in sequential and combinational CMOS circuits
    Semenov, O
    Sachdev, M
    2000 IEEE INTERNATIONAL WORKSHOP ON DEFECT BASED TESTING, PROCEEDINGS, 2000, : 36 - 41
  • [37] The impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness
    Semenov, O
    Sarbishaei, H
    Axelrad, V
    Sachdev, M
    MICROELECTRONICS RELIABILITY, 2004, 44 (9-11) : 1817 - 1822
  • [38] The impact of device footprint scaling on high-performance CMOS logic technology
    Deng, Jie
    Kim, Keunwoo
    Chuang, Ching-Te
    Wong, H.-S. Philip
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (05) : 1148 - 1155
  • [39] Impact of Technology Scaling on Performance of Domino Logic in Nano-Scale CMOS
    Guar, Abhishek
    Mahmoodi, Hamid
    2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), 2012, : 295 - 298
  • [40] An investigation on RF CMOS stability related to bias and scaling
    Su, JG
    Wong, SC
    Chang, CY
    SOLID-STATE ELECTRONICS, 2002, 46 (04) : 451 - 458
12345