Triple-Stacked Wafer-to-Wafer Hybrid Bonding for 3D Structured Image Sensors

被引:0
|
作者
Honda, Yuki [1 ]
Goto, Masahide [1 ]
Watabe, Toshihisa [1 ]
Nanba, Masakazu [1 ]
Iguchi, Yoshinori [1 ]
Saraya, Takuya [2 ]
Kobayashi, Masaharu [2 ]
Higurashi, Eiji [2 ]
Toshiyoshi, Hiroshi [2 ]
Hiramoto, Toshiro [2 ]
机构
[1] NHK Sci & Technol Res Labs, Setagaya Ku, 1-10-11 Kinuta, Tokyo 1578510, Japan
[2] Univ Tokyo, Meguro Ku, 4-6-1 Komaba, Tokyo 1538505, Japan
关键词
ELECTRODES;
D O I
10.23919/ltb-3d.2019.8735257
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose a triple-stacked wafer-to-wafer hybrid bonding technique for image sensor 3D integration by repeating (1) embedment of gold electrode sites, (2) Au/SiO2 bonding with a thin Si layer in between, and (3) subsequent lost-wafer processes.
引用
收藏
页码:45 / 45
页数:1
相关论文
共 50 条
  • [31] Reliability Challenges in Advanced 3D Technologies: The Case of Through Silicon Vias and SiCN-SiCN Wafer-to-Wafer Hybrid-Bonding Technologies
    Chery, Emmanuel
    Fohn, Corinna
    De Messemaeker, Joke
    Beyne, Eric
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2023, 23 (04) : 615 - 622
  • [32] Low Temperature Hybrid Wafer Bonding for 3D Integration
    Damian, A. A.
    Poelma, R. H.
    van Zeijl, H. W.
    Zhang, G. Q.
    2013 14TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2013,
  • [33] 300-mm Wafer 3D Integration Technology using Hybrid Wafer Bonding
    Hozawa, Kazuyuki
    Aoki, Mayu
    Hanaoka, Yuko
    Takeda, Kenichi
    2013 8TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2013, : 51 - 54
  • [34] Simulation of device structure impacts on bonding wave and strain in Wafer-to-Wafer Cu-Cu Hybrid Bonding
    Hirano, Takaaki
    Yamada, Taichi
    Kobayashi, Shoji
    Hagimoto, Yoshiya
    Iwamoto, Hayato
    2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, : 1314 - 1318
  • [35] Study of Ultra-Fine 0.4 μm Pitch Wafer-to-Wafer Hybrid Bonding and Impact of Bonding Misalignment
    Ikegami, Yukako
    Onodera, Takumi
    Chiyozono, Masanori
    Sakamoto, Akihisa
    Shimizu, Kan
    Kagawa, Yoshihisa
    Iwamoto, Hayato
    PROCEEDINGS OF THE IEEE 74TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC 2024, 2024, : 299 - 304
  • [36] 0.5 μm Pitch Wafer-to-wafer Hybrid Bonding at Low Temperatures with SiCN Bond Layer
    Ma, Kai
    Bekiaris, Nikolaos
    Hsu, Ching-Hsiang
    Xue, Lei
    Ramaswami, Sesh
    Ding, Taotao
    Probst, Gernot
    Wernicke, Tobias
    Uhrmann, Thomas
    Wimplinger, Markus
    PROCEEDINGS OF THE IEEE 74TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC 2024, 2024, : 331 - 336
  • [37] Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration
    Reda, Sherief
    Smith, Gregory
    Smith, Larry
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (09) : 1357 - 1362
  • [38] Scaling Cu/SiCN Wafer-to-Wafer Hybrid Bonding down to 400 nm interconnect pitch
    Zhang, Boyao
    Chew, Soon-Aik
    Stucchi, Michele
    Dewilde, Sven
    Iacovo, Serena
    Witters, Liesbeth
    Webers, Tomas
    Van Sever, Koen
    De Vos, Joeri
    Miller, Andy
    Beyer, Gerald
    Beyne, Eric
    PROCEEDINGS OF THE IEEE 74TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC 2024, 2024, : 312 - 318
  • [39] 3D Integration by Wafer-Level Aligned Wafer Bonding
    Dragoi, V.
    Burggraf, J.
    Kurz, F.
    Rebhan, B.
    2015 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 2015, : 185 - 188
  • [40] Results on Aligned SiO2/SiO2 Direct Wafer-to-Wafer Low Temperature Bonding for 3D Integration
    Garnier, A.
    Angermayer, M.
    Di Cioccio, L.
    Gueguen, P.
    Wagenleitner, T.
    2009 IEEE INTERNATIONAL SOI CONFERENCE, 2009, : 101 - +