CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems

被引：12

作者：

Yamaoka, Masanao ^{[1
]}

Okuyama, Takuya ^{[1
]}

Hayashi, Masato ^{[1
]}

Yoshimura, Chihiro ^{[1
]}

Takemoto, Takashi ^{[1
]}

机构：

[1] Hitachi Ltd, Ctr Technol Innovat Elect, Res & Dev Grp, Tokyo, Japan

来源：

2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2019年

关键词：

combinational optimization problems; Ising model; CMOS annealing machine; in-memory computing;

D O I：

10.1109/CICC.2019.8780296

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new computing architecture, an annealing machine, which is specialized to solve combinatorial optimization problems, is proposed. The annealing machine maps optimization problems to an Ising model and solves the optimization problems by its own convergence property. We proposed a CMOS implementation of the annealing machine, which is a type of an in-memory computing. We constructed two prototypes of the CMOS annealing machine. The 1st-generation prototype confirmed the power efficiency is 1800-times higher than that of the conventional von-Neumann computers. The FPGA 2md-generation prototype is used to explore its applications and is also confirmed its multiple-chip operation.

引用

页数：8

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