Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout Circuits

被引：0

作者：

Chen, C. L. ^{[1
]}

Yost, D-R. ^{[1
]}

Knecht, J. M. ^{[1
]}

Chapman, D. C. ^{[1
]}

Oakley, D. C. ^{[1
]}

Mahoney, L. J. ^{[1
]}

Donnelly, J. P. ^{[1
]}

Soares, A. M. ^{[1
]}

Suntharalingam, V. ^{[1
]}

Berger, R. ^{[1
]}

Bolkhovsky, V. ^{[1
]}

Hu, W. ^{[1
]}

Wheeler, B. D. ^{[1
]}

Keast, C. L. ^{[1
]}

Shaver, D. C. ^{[1
]}

机构：

[1] MIT, Lincoln Lab, Cambridge, MA 02139 USA

来源：

2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION | 2009年

关键词：

TECHNOLOGY; CMOS;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work; we modified our wafer-scale 3D integration technique, originals, developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diamerer InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-mu m pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.

引用

页码：252 / 255

页数：4

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