Modified Scan Flip-Flop for Low Power Testing

被引：16

作者：

Mishra, Amit ^{[1
]}

Sinha, Nidhi ^{[1
]}

Satdev ^{[1
]}

Singh, Virendra ^{[1
]}

Chakravarty, Sreejit ^{[2
]}

Singh, Adit D. ^{[3
]}

机构：

[1] Indian Inst Sci, Bangalore 560012, Karnataka, India

[2] LSI Corp, Milpitas, CA USA

[3] Auburn Univ, Auburn, AL 36849 USA

来源：

2010 19TH IEEE ASIAN TEST SYMPOSIUM (ATS 2010) | 2010年

关键词：

Low power testing; Launch on capture; Launch on shift; Stuck-at faults; Scan flip-flop;

D O I：

10.1109/ATS.2010.69

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal operation. In this paper, we propose a modified design of a scan flip-flop which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on performance. The new scan flip-flop disables the slave latch during scan, and uses an alternate low cost dynamic latch in the scan path instead. Methods for generating slave latch disable control signal are also presented.

引用

页码：367 / 370

页数：4

共 50 条

[41] A novel low power flip-flop design using footless scheme
Jin-Fa Lin
Ming-Yan Tsai
Ching-Sheng Chang
Yu-Ming Tsai
Analog Integrated Circuits and Signal Processing, 2018, 97 : 365 - 370
[42] Low-power half-static flip-flop structure
Manolescu, M
Lin, IP
2000 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, CAS 2000 PROCEEDINGS, 2000, : 211 - 214
[43] Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost
Cai, Hao
Wang, You
Naviner, Lirida Alves de Barros
Zhao, Weisheng
IEEE TRANSACTIONS ON MAGNETICS, 2016, 52 (08)
[44] Low Power Conditional Pulse Control with Transmission Gate Flip-Flop
Berwal, Deepak
Kumar, Ashish
Kumar, Yogendera
2015 INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION & AUTOMATION (ICCCA), 2015, : 1358 - 1362
[45] Flip-flop chaining architecture for power-efficient scan during test application
Gupta, S
Vaish, T
Chattopadhyay, S
14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 410 - 413
[46] Low power flip-flop with clock gating on master and slave latches
Strollo, AGM
De Caro, D
ELECTRONICS LETTERS, 2000, 36 (04) : 294 - 295
[47] A Low-Power CMOS Flip-Flop for High Performance Processors
Meher, Preetisudha
Mahapatra, Kamala Kanta
TENCON 2014 - 2014 IEEE REGION 10 CONFERENCE, 2014,
[48] Ultra-Low Power NAND Based Multiplexer And Flip-Flop
Varun, Ishan
Gupta, Tarun Kumar
2013 4TH NIRMA UNIVERSITY INTERNATIONAL CONFERENCE ON ENGINEERING (NUICONE 2013), 2013,
[49] A novel low power flip-flop design using footless scheme
Lin, Jin-Fa
Tsai, Ming-Yan
Chang, Ching-Sheng
Tsai, Yu-Ming
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2018, 97 (02) : 365 - 370
[50] A Modified Static Contention Free Single Phase Clocked Flip-flop Design for Low Power Applications
Lin, Jin-Fa
Tsai, Ming-Yan
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18 (05) : 640 - 644

← 1 2 3 4 5 →